1. Field of the Invention
The present invention relates to electrical semiconductor devices and, more particularly, to high voltage protection diodes having superior resistance to breakdown and superior clamping voltage characteristics when exposed to reverse voltages, and to a method of fabricating such electrical semiconductor devices.
2. Background
High voltage diodes require a high resistivity/low conductivity layer of sufficient thickness and resistivity to effectively block high reverse voltages and reverse currents. Furthermore, the design of such diodes desirably controls and minimizes the electric field at the edges of the diodes.
Prior art attempts at creating high voltage diodes capable of guarding against high reverse voltage or reverse current spikes have met with limited success. With the exception of a few manufacturers using costly processes, high voltage diodes known in the industry are only rated to withstand reverse voltages of 1600V, while sophisticated electronics applications frequently require diodes that can handle reverse voltages in excess of 1700V. Consequently, manufacturers of the more exotic electrical hardware must resort to testing a batch of 1600V diodes and selecting the few which exceed their rating and can meet the electrical parameters demanded by the hardware. Naturally, this leads to manufacturing delays and increased expense.
Typically, these diodes are formed by epitaxially growing a low conductivity layer onto a high conductivity substrate. Thereafter, a silicon oxide, (SiO2) mask is created by covering the exposed surface of the epitaxial layer with SiO2 and etching the SiO2 layer to expose a predetermined portion of the epitaxial surface. The portion to be exposed is predetermined in that the pattern is selected prior to beginning production of the device. A high conductivity layer is then diffused into the epitaxial layer creating deeper diffused regions where the SiO2 has been etched away and shallower diffused regions where the SiO2 remains. This results in a device with improved control of and which minimizes the electric field at the device edges. However, this known process for creating a dopant high conductivity layer involving applying and etching an SiO2 layer to create a mask through which the dopant high conductivity layer is diffused into the low conductivity layer is time consuming, expensive, and somewhat inexact.
Generally, the quality of the high voltage diode is proportional to the degree to which the low conductivity layer is free of contamination and defects. The extent to which an epitaxially-grown layer is free of defects is related to the rate at which it is grown. Generally, the slower the rate of epitaxial growth, the fewer the number of defects that are introduced into epitaxial layer.
In practice, the growth rate necessary to create an epitaxial layer sufficiently defect-free to function effectively as a low conductivity layer is three times the epitaxial growth rate necessary for the epitaxial layer to function effectively as a high conductivity layer. The increase in the time necessary to grow a low conductivity epitaxial layer translates into a production expense that significantly increases cost.
Alternatively, directly etched, entirely diffused semiconductor structures known in the art avoid the aforementioned problems. These devices are created by directly etching one surface of a low conductivity substrate and diffusing a high conductivity dopant layer therein, and diffusing an oppositely charged, high conductivity layer into the opposing substrate surface to create a P/N junction. However, the optimum depth of the diffused layers is too thin to structurally maintain a wafer intact when moats are etched in one surface of the wafer, as is necessary to create multiple devices on a single wafer. Increasing the depth of a diffused layer in an attempt to improve structural strength sufficiently to prevent a multiple-device wafer from crumbling during moat etch can cause the wafer to warp, making it more difficult to process, and leading to an unacceptably high rate of waste from breakage. Further, the boundary between the layers of a diffused P/N junction is more graded than the boundary between the layers of an epitaxially-grown P/N junction, resulting in an increased forward voltage drop across the device. Typically, the forward voltage drop across a diffused structure can be as high as 5V, while that of an epitaxial structure is as low as 1.7V for fast switching devices. Consequently, entirely diffused devices yield less attractive physical and electrical parameters.
The device of the present invention includes an electrical semiconductor appliance having a substrate of doped material on which a layer of oppositely doped material is epitaxially grown to form a P/N junction. The defects typically encountered during rapid epitaxial growth do not adversely affect the electrical performance of a semiconductor device when the defects are confined to a high conductivity region of the device. Therefore, in a preferred embodiment, the epitaxial layer is positioned to function as the high conductivity region of the P/N junction, resulting in an epitaxial layer that can be grown three times more rapidly than when it is positioned to function as the low conductivity region of the P/N junction.
In another aspect of the invention and irrespective of whether the epitaxial layer is positioned to function as the high conductivity region, the exposed surface of the low conductivity layer of the P/N junction is directly masked and etched via a photo-resist process. A high conductivity layer is then diffused into the etched surface of the low conductivity layer.
The time delay and expense of applying an SiO2 layer, the expense and waste incurred by etching a mask through the SiO2 layer and, ultimately, by removing the SiO2 mask, and the resultant diffusion depths that are inexact and inconsistent due to the unavoidably irregular thicknesses of the SiO2 layer are thereby avoided.
Also irrespective of whether the epitaxial layer functions as the high conductivity region, in a preferred embodiment germanium is permeated throughout the epitaxial layer during formation of the P/N junction, i.e., during the growth stage of the epitaxial layer, to serve as a stress-relieving dopant to counter the stress caused by the lattice mismatch between a lightly doped silicon and heavily boron doped silicon. As a result, warpage is reduced and breakage of wafers containing a plurality of the devices of the present invention is minimized, and it becomes economically feasible to produce wafers of increased diameter.
It is therefore an object of the present invention to provide improved high voltage electrical semiconductor devices achieved by providing reduced electrical field strengths at their perimeters.